With the rapid development of computer technologies and rapid increase in the speed of network lines, handling TCP/IP packets has been an increasingly complex workload on a computer system. For example, the speed of Ethernet lines tends to reach and even exceed 40 Gb/s, therefore, how to effectively deal with a task of receiving and/or transmitting packets at a high or very high speed has been a pressing problem that needs to be addressed.
There are generally two methods for a network interface card (NIC) to communicate with a processor, i.e., polling and interrupt, but the interruption method is the predominant method for communication. Processing of an interrupt handler actually involves a packet handling method. When the network interface card has packets to be handled by the processor, it delivers packets data into a kernel buffer via Direct Memory Access (DMA), thereby raising an interrupt; the processor switches to a kernel mode in which the processor executes an Interrupt Service Routine (ISR), responds to the interrupt and then returns to a preempted execution point while leaving handling of the packets as a process-level task. Interrupt-driven packet handling can work well in the case of a low frequency of NIC interrupts. However, the processor may suffer from a “livelock” phenomenon upon arrival of a large number of interrupts, which means that the processor can neither be hung up nor process any user program.
Various methods have been proposed for effectively implementing interrupts in a computer system. For example, methods of Interrupt Coalition (primarily applicable to reception of packets, in which several packets are received at a time before an interrupt arises), Hybrid Polling-Interrupt, TCP Offload Engine (TOE), Remote Direct Memory Access (RDMA)/Direct Data Placement (DDP), are several effective solutions proposed in recent years. However, both of the methods of Interrupt Coalition and Hybrid Polling-Interrupt have an undetermined latency, while an aggressive modification to the NIC and kernel is required for the methods of TOE and RDMA, which may not be welcomed by hardware or software developers. Additionally, a TOE-enabled NIC, i.e., TOE NIC, may incur a relatively high cost.
Multi-core processors have been a commonly acknowledged trend of processor designs since the birth of multi-core technologies. Furthermore, the frequency of NIC interrupts has increased with the rapid increase in the speed of network lines. Taking Ethernet as an example, when the line speed is increased to 40 Gb/s, for packets with a maximum size of 1500 bytes, an interruption rate (i.e., the number of interrupts per unit time) is 3200000/s in the case of no Interrupt Coalition, and even in the case of Interrupt Coalition with a coalition factor of 10, the interruption rate is still 320000/s, which may overwhelm a 5 GHz P6 CPU. In a multi-core processor environment, however, each core merely has moderate handling capability and is not powerful enough to handle interrupts at such a high frequency, that is, arriving interrupts have to be dispatched to a plurality of cores for handling. Furthermore, a workload in a core may vary from one core to another in an operating multi-core processor, that is, it may take different times for different cores to handle an interrupt. Control dependency may exist between sequentially arriving packets but with low data dependency therebetween, and those packets transmitted from the NIC are unlikely corrupted packets which need to be retransmitted. Therefore, cache affinity has to be considered for dispatching interrupts (especially NIC interrupts) arriving from the outside to a plurality of cores.
FIG. 1 illustrates a typical multi-core environment. As shown in FIG. 1, a multi-core processor 120 includes an interrupt dispatcher 130 and K cores 140 (denoted respectively by Core 1, Core 2, . . . , Core K) each of which is connected directly with the interrupt dispatcher 130 via a bus. An interrupt signal arriving from the outside, e.g., an I/O interrupt, an NIC interrupt, is sent to the interrupt dispatcher 130 in the multi-core processor 120 via a Programmable Interrupt Controller (PIC) 110, and then the interrupt dispatcher 130 selects or determines one of the K cores 140 as a hot core randomly or according to a predetermined rule (e.g., based upon interrupt priorities and so on.) in accordance with an interrupt identifier (i.e., interrupt ID) and sends the interrupt signal to the hot core for handling.
None of the existing interrupt dispatching methods has considered the issue of workload varying from one core to another or the issue of cache affinity and consequently cannot provide optimized processor performance capable of effective interrupt handling. Therefore, there is a pressing need of an effective interrupt dispatching mechanism in a multi-core environment.